1. Field of the Invention
The invention relates generally to trapped charge within semiconductor devices. More particularly, the invention relates to structures and methods for dissipating trapped charge within semiconductor devices.
2. Description of the Related Art
Semiconductor circuits, including CMOS circuits, are often susceptible to ionizing radiation that may lead to trapped charge within layers such as dielectric layers. Trapped charge in a gate dielectric may cause changes in field effect transistor operating parameters, such as a threshold voltage shift. Threshold voltage shifts large enough in magnitude can lead to inoperability of a field effect transistor since a gate may no longer effectively control a channel, due to the presence of trapped charge.
In addition, trapped charge within a dielectric isolation region may make operative a sidewall device or otherwise create a leakage pathway between devices within a semiconductor structure.
Thermal annealing heaters and thermal annealing methods are known in the art to dissipate trapped charge within dielectric layers. Examples include: (1) Kelleher et al., in “Investigation of On-chip High Temperature Annealing of PMOS Dosimeters,” IEEE Trans on Nuclear Science, Vol. 43(3), June 1996, pp. 997-1001 (a polysilicon resistor that surrounds a radiation sensitive field effect transistor (RADFET)); (2) Chabrerie et al., in “A New Integrated Test Structure for on-chip Post Irradiation Annealing in MOS Devices,” IEEE Trans on Nuclear Science, 45, 1438 (1998) (on chip heating for trapped charge dissipation within the context of silicon-on-insulator technology); and (3) Takahiro et al., Patent Abstracts of Japan No. 60-055654 (radiation resistance of an integrated circuit effected using a heat generating circuit).
Semiconductor structure dimensions are certain to continue to decrease. As a result thereof, consideration of trapped charge generation and control within semiconductor devices is also likely of considerable importance. To that end, structures and methods for trapped charge dissipation within semiconductor structures are desirable.